`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:02:10 11/20/2013
// Design Name:   cavlc_nc_negone_lut
// Module Name:   G:/Xilinx_Proj/H_264_test/nc_negone_lut_test.v
// Project Name:  H_264_test
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: cavlc_nc_negone_lut
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module nc_negone_lut_test;

	// Inputs
	reg [7:0] data;

	// Outputs
	wire [2:0] Tls;
	wire [4:0] TotalCoeff;
	wire [4:0] Bits;
	
	reg clk,rst;
	reg [8:0] cnt;
	// Instantiate the Unit Under Test (UUT)
	cavlc_nc_negone_lut uut (
		.data(data), 
		.Tls(Tls), 
		.TotalCoeff(TotalCoeff), 
		.Bits(Bits)
	);

	initial begin
		// Initialize Inputs
		data = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		#100 rst=1; 
		 #100 rst=0; 
		 #100 rst=1; 
		 clk=0;
		 cnt=0;
	end
      
always begin #50 clk=~clk; end
  
always @(negedge rst or posedge clk) begin
		if(!rst) begin
			cnt<=0;
		end
		else begin
			case(cnt)
			0:begin
				data<=16'b0000000000000010;cnt<=cnt+1'b1;
			end
			1:begin
				data<=16'b0000000000111000;cnt<=cnt+1'b1;
			end
			2:begin
				data<=16'b0000000000000001;cnt<=cnt+1'b1;
			end
			3:begin
				data<=16'b0000000000001000;cnt<=cnt+1'b1;
			end
			4:begin
				data<=16'b0000000000011000;cnt<=cnt+1'b1;
			end
			5:begin
				data<=16'b0000000000000100;cnt<=cnt+1'b1;
			end
			6:begin
				data<=16'b0000000000110000;cnt<=cnt+1'b1;
			end
			7:begin
				data<=16'b0000000001100000;cnt<=cnt+1'b1;
			end
			8:begin
				data<=16'b0000000000100000;cnt<=cnt+1'b1;
			end
			9:begin
				data<=16'b0000000000101000;cnt<=cnt+1'b1;
			end
			10:begin
				data<=16'b0000000000010000;cnt<=cnt+1'b1;
			end
			11:begin
				data<=16'b0000000011000000;cnt<=cnt+1'b1;
			end
			12:begin
				data<=16'b0000000001000000;cnt<=cnt+1'b1;
			end
			13:begin
				data<=16'b0000000000000000;cnt<=cnt+1'b1;;
			end
			14:begin
				data<=16'b0000000000000000;cnt<=7'd14;
			end
			endcase
		end
end			
		
		
endmodule

